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1CY 7C24 5A
CY7C245A
2K x 8 Reprogrammable Registered PROM
Features
* Windowed for reprogrammability * CMOS for optimum speed/power * High speed -- 15-ns address set-up -- 10-ns clock to output * Low power -- 330 mW (commercial) for -25 ns -- 660 mW (military) * Programmable synchronous or asynchronous output enable * On-chip edge-triggered registers * Programmable asynchronous register (INIT) * EPROM technology, 100% programmable * Slim, 300-mil, 24-pin plastic or hermetic DIP * 5V 10% VCC, commercial and military * TTL-compatible I/O * Direct replacement for bipolar PROMs * Capable of withstanding greater than 2001V static discharge
Functional Description
The CY7C245A is a high-performance, 2K x 8, electrically programmable, read only memory packaged in a slim 300-mil plastic or hermetic DIP. The ceramic package may be equipped with an erasure window; when exposed to UV light the PROM is erased and can then be reprogrammed. The memory cells utilize proven EPROM floating-gate technology and byte-wide intelligent programming algorithms. The CY7C245A replaces bipolar devices and offers the advantages of lower power, reprogrammability, superior performance and high programming yield. The EPROM cell requires only 12.5V for the supervoltage, and low current requirements allow gang programming. The EPROM cells allow each memory location to be tested 100%, because each location is written into, erased, and repeatedly exercised prior to encapsulation. Each PROM is also tested for AC performance to guarantee that after customer programming the product will meet AC specification limits. The CY7C245A has an asynchronous initialize function (INIT). This function acts as a 2049th 8-bit word loaded into the on-chip register. It is user programmable with any desired word, or may be used as a PRESET or CLEAR function on the outputs. INIT is triggered by a low level, not an edge.
Logic Block Diagram
INIT A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 CP COLUMN ADDRESS ADDRESS DECODER ROW ADDRESS PROGRAMMABLE ARRAY MULTIPLEXER O5 8-BIT EDGETRIGGERED REGISTER O4 O3 O2 O1 O0 O7 O6
PinConfigurations
DIP Top View
A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC A8 A9 A10 INIT E/ES CP O7 O6 O5 O4 O3
C245A-2
LCC/PLCC (Opaque only) Top View
4 3 2 1 282726 25 5 24 6 23 7 22 8 21 9 20 10 19 11 1314151617 18 12 A10 INIT E/ES CP NC O7 O6 C245A-3
E/E
S
D C
Q
PROGRAMMABLE MULTIPLEXER
CP
A4 A3 A2 A1 A0 NC O0
C245A-1
Selection Guide
7C245A-15 15 10 120 7C245A-18 18 12 120 120 7C245A-25 7C245AL-25 25 12 90 120 60 7C245A-35 7C245AL-35 35 15 90 120 60 7C245A-45 7C245AL-45 45 25 90 120 60
Minimum Address Set-Up Time (ns) Maximum Clock to Output (ns) Maximum Operating Standard Commercial Current (mA) Military L Commercial
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 August 1987 - Revised May 1994
CY7C245A
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .....................................-65C to +150C Ambient Temperature with Power Applied..................................................-55C to +125C Supply Voltage to Ground Potential (Pin 24 to Pin 12).................................................-0.5V to +7.0V DC Voltage Applied to Outputs in High Z State .....................................................-0.5V to +7.0V DC Input Voltage .................................................-3.0V to +7.0V DC Program Voltage (Pins 7, 18, 20) ........................... 13.0V UV Erasure................................................... 7258 Wsec/cm 2 Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 mA
Operating Range
Range Commercial Industrial[1] Military[2] Ambient Temperature 0C to +70C -40C to +85C -55C to +125C VCC 5V 10% 5V 10% 5V 10% 7C245AL-25 7C245AL-35 7C245AL-45 Min. 2.4 0.4 2.0 VCC 0.8 -10 +10 -10 2.0 0.4 VCC 0.8 +10 Max. Unit V V V V A
Electrical Characteristics Over the Operating Range
[3,4]
7C245A-25 7C245A-35 7C245A-15 7C245A-18 7C245A-45 Parameter VOH VOL VIH VIL IIX VCD IOZ IOS ICC VPP IPP VIHP VILP
]
Description
Test Conditions
Min. Max. Min. Max. Min. 2.4 0.4 2.0 VCC 0.8 -10 +10 -10 Note 4 2.0 2.4 0.4 VCC 0.8 +10 2.4
Max.
Output HIGH Voltage VCC = Min., IOH = -4.0 mA VIN = VIH or VIL Output LOW Voltage Input HIGH Level Input LOW Level VCC = Min., IOL = 16 mA VIN = VIH or VIL Guaranteed Input Logical HIGH Voltage for All Inputs Guaranteed Input Logical LOW Voltage for All Inputs
Input Leakage Current GND < VIN < VCC Input Clamp Diode Voltage Output Leakage Current Output Short Circuit Current GND < VO < VCC Output Disabled[5] VCC = Max., VOUT =0.0V[6] Com'l Mil
-10 -20
+10 -90 120
-10 -20
+10 -90 120 120
-10 -20
+10 -90 90 120
-10 -20
+10 -90 60
A mA mA V mA V
Power Supply Current VCC = Max., IOUT=0 mA Programming Supply Voltage Programming Supply Current Input HIGH Programming Voltage Input LOW Programming Voltage
12
13 50
12
13 50
12
13 50
12
13 50
3.0 0.4
3.0 0.4
3.0 0.4
3.0 0.4
V
Capacitance[4]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 10 10 Unit pF pF
Notes: 1. Contact a Cypress representative for industrial temperature range specifications. 2. TA is the "instant on" case temperature. 3. See the last page of this specification for Group A subgroup testing information. 4. See the "Introduction to CMOS PROMs" section of the Cypress Data Book for general information on testing. 5. For devices using the synchronous enable, the device must be clocked after applying these voltages to perform this measurement. 6. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
2
CY7C245A
AC Test Loads and Waveforms[3, 4]
5V OUTPUT 50 pF INCLUDING JIG AND SCOPE R2 167 R1 250 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 167 R1 250 3.0V GND 5 ns
C245A-4
ALL INPUT PULSES 90% 10% 90% 10% 5 ns
C245A-5
(a) Normal Load
(b) High Z Load
Equivalent to: TH EVENIN EQUIVALENT 100 OUTPUT 2.0V
C245A-6
Switching Characteristics Over Operating Range[3, 4]
7C245A-15 Parameter tSA tHA tCO tPWC tSES tHES tDI tRI tPWI tCOS tHZC tDOE tHZE Description Address Set-Up to Clock HIGH Address Hold from Clock HIGH Clock HIGH to Valid Output Clock Pulse Width ES Set-Up to Clock HIGH ES Hold from Clock HIGH Delay from INIT to Valid Output INIT Recovery to Clock HIGH INIT Pulse Width Valid Output from Clock HIGH[7] Inactive Output from Clock HIGH[7] Valid Output from E LOW[8] Inactive Output from E HIGH[8] 10 10 15 15 12 15 10 10 5 15 12 12 15 15 15 15 Min. 15 0 10 12 10 5 20 15 15 15 15 15 15 Max. 7C245A-18 Min. 18 0 12 15 12 5 20 20 20 20 20 20 20 Max. 7C245A-35 Min. 25 0 12 20 15 5 20 20 25 30 30 30 30 Max. 7C245A-25 7C245AL-25 Min. 35 0 15 20 15 5 35 Max. 7C245A-35 7C245AL-35 Min. 45 0 25 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 7. Applies only when the synchronous (ES) function is used. 8. Applies only when the asynchronous (E) function is used.
Operating Modes
The CY7C245A is a CMOS electrically programmable read only memory organized as 2048 words x 8 bits and is a pin-for-pin replacement for bipolar TTL fusible link PROMs. The CY7C245A incorporates a D-type, master-slave register on chip, reducing the cost and size of pipelined microprogrammed systems and applications where accessed PROM data is stored temporarily in a register. Additional flexibility is provided with a programmable synchronous (ES) or asynchronous (E) output enable and asynchronous initialization (INIT). Upon power-up the state of the outputs will depend on the programmed state of the enable function (ES or E). If the synchronous enable (ES) has been programmed, the register will be in the set condition causing the outputs (O0 - O7) to be in the OFF or high-impedance state. If the asynchronous enable (E) is being used, the outputs will come up in the OFF or high-impedance state only if the enable (E) input is at a HIGH logic level. Data is read by applying the memory location to the address inputs (A0 - A10) and a logic
LOW to the enable input. The stored data is accessed and loaded into the master flip-flops of the data register during the address set-up time. At the next LOW-to-HIGH transition of the clock (CP), data is transferred to the slave flip-flops, which drive the output buffers, and the accessed data will appear at the outputs (O0 - O7). If the asynchronous enable (E) is being used, the outputs may be disabled at any time by switching the enable to a logic HIGH, and may be returned to the active state by switching the enable to a logic LOW. If the synchronous enable (ES) is being used, the outputs will go to the OFF or high-impedance state upon the next positive clock edge after the synchronous enable input is switched to a HIGH level. If the synchronous enable pin is switched to a logic LOW, the subsequent positive clock edge will return the output to the active state. Following a positive clock edge, the address and synchronous enable inputs are free to change since no change in the output will occur until the next LOW-to-HIGH transition of the clock. This unique feature allows the CY7C245A decoders and sense amplifiers to access the next location while previously addressed data remains stable on the outputs.
3
CY7C245A
Operating Modes (Continued)
System timing is simplified in that the on-chip edge triggered register allows the PROM clock to be derived directly from the system clock without introducing race conditions. The on-chip register timing requirements are similar to those of discrete registers available in the market. The CY7C245A has an asynchronous initialize input (INIT). The initialize function is useful during power-up and time-out sequences and can facilitate implementation of other sophisticated functions such as a built-in "jump start" address. When activated, the initialize control input causes the contents of a user-programmed 2049th 8-bit word to be loaded into the on-chip register. Each bit is programmable and the initialize function can be used to load any desired combination of 1s and 0s into the register. In the unprogrammed state, activating INIT will generate a register CLEAR (all outputs LOW). If all the bits of the initialize word are programmed, activating INIT performs a register PRESET (all outputs HIGH). Applying a LOW to the INIT input causes an immediate load of the programmed initialize word into the master and slave flip-flops of the register, independent of all other inputs, including the clock (CP). The initialize data will appear at the device outputs after the outputs are enabled by bringing the asynchronous enable (E) LOW.
Switching Waveforms[4]
tHA A0 - A10 tSES ES tSES tHES tHES tSES tHES tSA tHA
CP
tPWC tPWC
tPWC tPWC
tPWC tPWC
O0 - O7 tCO tHZC tCOS tCO tHZE E tDI INIT tPWI tRI tDOE
C245A-7
Erasure Characteristics
Wavelengths of light less than 4000 Angstroms begin to erase the 7C245A. For this reason, an opaque label should be placed over the window if the PROM is exposed to sunlight or fluorescent lighting for extended periods of time. The recommended dose for erasure is ultraviolet light with a wavelength of 2537 Angstroms for a minimum dose (UV intensity multiplied by exposure time) of 25 Wsec/cm2. For an ultraviolet lamp with a 12 mW/cm2 power rating the exposure time would be approximately 35 minutes. The 7C245A needs to be within 1 inch of the lamp during erasure. Permanent damage may result if the PROM is exposed to high-intensity UV light for an extended period of time. 7258 Wsec/cm2 is the recommended maximum dosage.
ages, please see the PROM Programming Information located at the end of this section. Programming algorithms can be obtained from any Cypress representative.
Bit Map Data
Programmer Address Decimal Hex 0 0 . . . . . . 2047 7FF 2048 800 2049 801 Control Byte 00 ............ Asynchronous output enable (default state) 01 ..................................... Synchronous output enable RAM Data Contents Data . . . Data Init Byte Control Byte
Programming Information
Programming support is available from Cypress as well as from a number of third-party software vendors. For detailed programming information, including a listing of software pack-
4
CY7C245A
Table 1. Mode Selection. Pin Function[9] Read or Output Disable Mode Read Output Disable Initialize Program Program Verify Program Inhibit Intelligent Program Program Synchronous Enable Program Initialization Byte Blank Check Zeros
Notes: 9. X = "don't care" but not to exceed VCC +5%.
Other
A10 - A4 A10 - A4 A10 - A4 A10 - A4 A10 - A4 A10 - A4 A10 - A4 A10 - A4 A10 - A4 A10 - A4 A10 - A4 A10 - A4
A3 A3 A3 A3 A3 A3 A3 A3 A3 VIHP VILP A3
A2 - A1 A2 - A1 A2 - A1 A2 - A1 A2 - A1 A2 - A1 A2 - A1 A2 - A1 A2 - A1 A2 - A1 A2 - A1 A2 - A1
A0 A0 A0 A0 A0 A0 A0 A0 A0 VPP VPP A0
CP PGM VIL/VIH X X VILP VIHP VIHP VILP VILP VILP VIHP
E, ES VFY VIL VIH VIL VIHP VILP VIHP VIHP VIHP VIHP VILP
INIT VPP VIH VIH VIL VPP VPP VPP VPP VPP VPP VPP
O7 - O0 D7 - D0 O7 - O0 High Z Init. Byte D7 - D0 O7 - O0 High Z D7 - D0 High Z D7 - D0 Zeros
DIP Top View
A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC A8 A9 A10 VPP VFY PGM D7 D6 D5 D4 D3 C245A-8
LCC/PLCC (Opaque Only) Top View
A4 A3 A2 A1 A0 NC D0
5 6 7 8 9 10 11
4 3 2 1 28 27 26 25 24 23 22 21 20 19 121314151617 18
A10 VPP VFY PGM NC D7 D6 C245A-9
Figure 1. Programming Pinouts.
5
CY7C245A
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.6 1.4 1.1 1.2 1.0 1.0 0.8 0.6 4.0 TA =25C f = fMAX 4.5 5.0 5.5 6.0 0.9 1.0 0.8 TA =25C 0.8 -55 25 125 0.6 4.0 4.5 5.0 5.5 6.0 1.2 NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 1.6 1.4 1.2 CLOCK TO OUTPUT TIME vs. VCC
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (C)
SUPPLY VOLTAGE (V)
CLOCK TO OUTPUT TIME vs. TEMPERATURE 1.6 1.4 1.2 0.8 1.0 0.8 0.6 -55 0.6 1.2 1.0
NORMALIZED SET-UP TIME vs. SUPPLYVOLTAGE 1.6 1.4 1.2 1.0 0.8 0.6 -55
NORMALIZED SET-UP TIME vs. TEMPERATURE
TA =25C 25 125 0.4 4.0 4.5 5.0 5.5 6.0
25
125
AMBIENT TEMPERATURE (C)
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (C)
NORMALIZED SUPPLY CURRENT vs. CLOCK PERIOD 1.02 1.00 0.98 0.96 0.94 0.92 0.90 0.88 0 25 50 75 100 15.0 10.0 5.0 0.0 VCC =5.5V TA =25C 30.0 25.0 20.0
TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 175 150 125 100 75 50 TA =25C VCC =4.5V 0 200 400 600 800 1000 25
OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE
VCC =5.0V TA =25C
0 0.0
1.0
2.0
3.0
4.0
CLOCK PERIOD (ns)
CAPACITANCE (pF)
OUTPUT VOLTAGE (V)
C245A-10
6
CY7C245A
Ordering Information[10]
Speed (ns) tSA tCO 15 10 ICC (mA) 120 Ordering Code CY7C245A-15JC CY7C245A-15PC CY7C245A-15WC CY7C245A-18JC CY7C245A-18PC CY7C245A-18WC CY7C245A-18DMB CY7C245A-18LMB CY7C245A-18QMB CY7C245A-18TMB CY7C245A-18WMB CY7C245AL-25PC CY7C245AL-25WC CY7C245A-25JC CY7C245A-25PC CY7C245A-25SC CY7C245A-25WC CY7C245A-25DMB CY7C245A-25LMB CY7C245A-25QMB CY7C245A-25TMB CY7C245A-25WMB CY7C245AL-35PC CY7C245AL-35WC CY7C245A-35JC CY7C245A-35PC CY7C245A-35SC CY7C245A-35WC CY7C245A-35DMB CY7C245A-35LMB CY7C245A-35QMB CY7C245A-35TMB CY7C245A-35WMB CY7C245A-45JC CY7C245A-45PC CY7C245A-45JC CY7C245A-45PC CY7C245A-45SC CY7C245A-45WC CY7C245A-45DMB CY7C245A-45LMB CY7C245A-45QMB CY7C245A-45TMB CY7C245A-45WMB Package Type J64 P13 W14 J64 P13 W14 D14 L64 Q64 T73 W14 P13 W14 J64 P13 S13 W14 D14 L64 Q64 T73 W14 P13 W14 J64 P13 S13 W14 D14 L64 Q64 T73 W14 J64 P13 J64 P13 S13 W14 D14 L64 Q64 T73 W14 Package Type 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 24-Lead (300-Mil) Windowed CerDIP 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 24-Lead (300-Mil) Windowed CerDIP 24-Lead (300-Mil) CerDIP 28-Square Leadless Chip Carrier 28-Pin Windowed Leadless Chip Carrier 24-Lead Windowed Cerpack 24-Lead (300-Mil) Windowed CerDIP 24-Lead (300-Mil) Molded DIP 24-Lead (300-Mil) Windowed CerDIP 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 24-Lead Molded SOIC 24-Lead (300-Mil) Windowed CerDIP 24-Lead (300-Mil) CerDIP 28-Square Leadless Chip Carrier 28-Pin Windowed Leadless Chip Carrier 24-Lead Windowed Cerpack 24-Lead (300-Mil) Windowed CerDIP 24-Lead (300-Mil) Molded DIP 24-Lead (300-Mil) Windowed CerDIP 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 24-Lead Molded SOIC 24-Lead (300-Mil) Windowed CerDIP 24-Lead (300-Mil) CerDIP 28-Square Leadless Chip Carrier 28-Pin Windowed Leadless Chip Carrier 24-Lead Windowed Cerpack 24-Lead (300-Mil) Windowed CerDIP 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 24-Lead Molded SOIC 24-Lead (300-Mil) Windowed CerDIP 24-Lead (300-Mil) CerDIP 28-Square Leadless Chip Carrier 28-Pin Windowed Leadless Chip Carrier 24-Lead Windowed Cerpack 24-Lead (300-Mil) Windowed CerDIP Operating Range Commercial
18
12
120
Commercial
Military
25
15
60 90
Commercial
120
Military
35
20
60 90
Commercial
120
Military
45
25
60 90
Commercial
120
Military
Notes: 10. Most of these products are available in industrial temperature range. Contact a Cypress representative for specifications and product availability.
7
CY7C245A
MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics
Parameter VOH VOL VIH VIL IIX IOZ ICC Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3
SMD Cross Reference
SMD Number 5962-88735 5962-88735 5962-88735 5962-88735 5962-88735 5962-88735 5962-88735 5962-88735 5962-88735 5962-88735 5962-88735 5962-88735 5962-87529 5962-87529 5962-87529 5962-87529 5962-87529 5962-87529 5962-89815 5962-89815 5962-89815 5962-89815 5962-89815 5962-89815 5962-89815 5962-89815 5962-89815 Suffix 01KX 01LX 013X 02KX 02LX 023X 03KX 03LX 033X 04KX 04LX 043X 01KX 01LX 013X 02KX 02LX 023X 01LX 01KX 013X 02LX 02KX 023X 03LX 03KX 033X Cypress Number CY7C245A-45KMB CY7C245A-45DMB CY7C245A-45LMB CY7C245A-35KMB CY7C245A-35DMB CY7C245A-35LMB CY7C245A-35KMB CY7C245A-35DMB CY7C245A-25LMB CY7C245A-25KMB CY7C245A-25DMB CY7C245A-25LMB CY7C245A-45TMB CY7C245A-45WMB CY7C245A-45QMB CY7C245A-35TMB CY7C245A-35WMB CY7C245A-35QMB CY7C245A-35WMB CY7C245A-35TMB CY7C245A-35QMB CY7C245A-25WMB CY7C245A-25TMB CY7C245A-25QMB CY7C245A-18WMB CY7C245A-18TMB CY7C245A-18QMB
Switching Characteristics
Parameter tSA tHA tCO Subgroups 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11
Document #: 38-00074-G
8
CY7C245A
Package Diagrams
24-Lead (300-Mil) CerDIP D14
MIL-STD-1835 D-9 Config.A
28-Lead Plastic Leaded Chip Carrier J64
28-Square Leadless ChipCarrier L64
MIL-STD-1835 C-4
28-Pin Windowed Leadless Chip Carrier Q64
MIL-STD-1835 C-4
9
CY7C245A
Package Diagrams (Continued)
24-Lead (300-Mil) Molded DIP P13/P13A
24-Lead (300-Mil) Molded SOIC S13
10
CY7C245A
Package Diagrams (Continued)
24-Lead (300-Mil) Windowed CerDIP W14
MIL-STD-1835 D-9 Config.A
(c) Cypress Semiconductor Corporation, 1994. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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